C9.6 Performance Monitors Configuration Register

The PMCFGR characteristics are:

Contains PMU specific configuration data.
Usage constraints

The accessibility to the PMCFGR by condition code is:

Error Error Error Error RO RO

C2.2 External register access permissions to the PMU registers describes the condition codes.

The PMCFGR is in the processor power domain.
See C9.5 Memory-mapped PMU register summary.
Figure C9-4 PMCFGR bit assignments
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Reserved, res0.

EX, [16]

Export supported. The value is:

1Export is supported. PMCR_EL0.EX is read/write.
CCD, [15]

Cycle counter has pre-scale. The value is:

1PMCR_EL0.D is read/write.
CC, [14]

Dedicated cycle counter supported. The value is:

1Dedicated cycle counter is supported.
Size, [13:8]

Counter size. The value is:

0b11111164-bit counters.
N, [7:0]

Number of event counters. The value is:

0x06Six counters.

The PMCFGR can be accessed through the external debug interface, offset 0xE00.

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