C9.8 Performance Monitors Peripheral Identification Register 0

The PMPIDR0 characteristics are:

Purpose
Provides information to identify a Performance Monitor component.
Usage constraints

The PMPIDR0 can be accessed through the external debug interface.

The accessibility to the PMPIDR0 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

C2.2 External register access permissions to the PMU registers describes the condition codes.

Configurations
The PMPIDR0 is in the Debug power domain.
Attributes
See the register summary in C9.5 Memory-mapped PMU register summary.
Figure C9-5 PMPIDR0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[31:8]

Reserved, res0.

Part_0, [7:0]
0xDB Least significant byte of the performance monitor part number.

The PMPIDR0 can be accessed through the external debug interface, offset 0xFE0.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.