C9.9 Performance Monitors Peripheral Identification Register 1

The PMPIDR1 characteristics are:

Purpose
Provides information to identify a Performance Monitor component.
Usage constraints

The PMPIDR1 can be accessed through the external debug interface.

The accessibility to the PMPIDR1 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

C2.2 External register access permissions to the PMU registers describes the condition codes.

Configurations
The PMPIDR1 is in the Debug power domain.
Attributes
See the register summary in C9.5 Memory-mapped PMU register summary.
Figure C9-6 PMPIDR1 bit assignments
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[31:8]

Reserved, res0.

DES_0, [7:4]
0xBARM Limited. This is the least significant nibble of JEP106 ID code.
Part_1, [3:0]
0x9Most significant nibble of the performance monitor part number.

The PMPIDR1 can be accessed through the external debug interface, offset 0xFE4.

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