C9.11 Performance Monitors Peripheral Identification Register 3

The PMPIDR3 characteristics are:

Purpose
Provides information to identify a Performance Monitor component.
Usage constraints

The PMPIDR3 can be accessed through the external debug interface.

The accessibility to the PMPIDR3 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

C2.2 External register access permissions to the PMU registers describes the condition codes.

Configurations
The PMPIDR3 is in the Debug power domain.
Attributes
See the register summary in C9.5 Memory-mapped PMU register summary.
Figure C9-8 PMPIDR3 bit assignments
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[31:8]

Reserved, res0.

REVAND, [7:4]
0x0Part minor revision.
CMOD, [3:0]
0x0Customer modified.

The PMPIDR3 can be accessed through the external debug interface, offset 0xFEC.

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