C9.12 Performance Monitors Peripheral Identification Register 4

The PMPIDR4 characteristics are:

Provides information to identify a Performance Monitor component.
Usage constraints

The PMPIDR4 can be accessed through the external debug interface.

The accessibility to the PMPIDR4 by condition code is:

- - - - RO RO

C2.2 External register access permissions to the PMU registers describes the condition codes.

The PMPIDR4 is in the Debug power domain.
See the register summary in C9.5 Memory-mapped PMU register summary.
Figure C9-9 PMPIDR4 bit assignments
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Reserved, res0.

Size, [7:4]
0x0Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.
DES_2, [3:0]
0x4ARM Limited. This is the least significant nibble JEP106 continuation code.

The PMPIDR4 can be accessed through the external debug interface, offset 0xFD0.

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