C9.17 Performance Monitors Component Identification Register 2

The PMCIDR2 characteristics are:

Purpose
Provides information to identify a Performance Monitor component.
Usage constraints

The PMCIDR2 can be accessed through the external debug interface.

The accessibility to the PMCIDR2 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

C2.2 External register access permissions to the PMU registers describes the condition codes.

Configurations
The PMCIDR2 is in the Debug power domain.
Attributes
See the register summary in C9.5 Memory-mapped PMU register summary.
Figure C9-12 PMCIDR2 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[31:8]

Reserved, res0.

PRMBL_2, [7:0]
0x05Preamble byte 2.

The PMCIDR2 can be accessed through the external debug interface, offset 0xFF8.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.