C9.18 Performance Monitors Component Identification Register 3

The PMCIDR3 characteristics are:

Purpose
Provides information to identify a Performance Monitor component.
Usage constraints

The PMCIDR3 can be accessed through the external debug interface.

The accessibility to the PMCIDR3 by condition code is:

Off DLK OSLK EPMAD SLK Default
- - - - RO RO

C2.2 External register access permissions to the PMU registers describes the condition codes.

Configurations
The PMCIDR3 is in the Debug power domain.
Attributes
See the register summary in C9.5 Memory-mapped PMU register summary.
Figure C9-13 PMCIDR3 bit assignments
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[31:8]

Reserved, res0.

PRMBL_3, [7:0]
0xB1Preamble byte 3.

The PMCIDR3 can be accessed through the external debug interface, offset 0xFFC.

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