C10.8 Event Control 1 Register

The TRCEVENTCTL1R characteristics are:

Controls the behavior of the events that TRCEVENTCTL0R selects.
Usage constraints
  • You must always program this register as part of trace unit initialization.
  • Accepts writes only when the trace unit is disabled.
Available in all configurations.

TRCEVENTCTL1R is a 32-bit RW trace register.

See C10.1 ETM register summary.

Figure C10-7 TRCEVENTCL1R bit assignments
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Reserved, res0.

Low-power state behavior override:

0Low-power state behavior unaffected.
1Low-power state behavior overridden. The resources and Event trace generation are unaffected by entry to a low-power state.
ATB, [11]

ATB trigger enable:

0ATB trigger disabled.
1ATB trigger enabled.
Reserved, res0.
EN, [3:0]

One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs:

0Event does not cause an event element.
1Event causes an event element.

The TRCEVENTCTL1R can be accessed through the external debug interface, offset 0x024.

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