C10.9 Stall Control Register

The TRCSTALLCTLR characteristics are:

Purpose
Enables the ETM trace unit to stall the Cortex®‑A32 processor if the ETM trace unit FIFO overflows.
Usage constraints
  • You must always program this register as part of trace unit initialization.
  • Accepts writes only when the trace unit is disabled.
Configurations
Available in all configurations.
Attributes
See C10.1 ETM register summary.
Figure C10-8 TRCSTALLCTLR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[31:9]
Reserved, res0.
ISTALL, [8]

Instruction stall bit. Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL:

0The trace unit does not stall the processor.
1The trace unit can stall the processor.
[7:4]
Reserved, res0.
LEVEL, [3:2]

Threshold level field. The field can support 4 monotonic levels from 0b00 to 0b11, where:

0b00Zero invasion. This setting has a greater risk of an ETM trace unit FIFO overflow.
0b11Maximum invasion occurs but there is less risk of a FIFO overflow.
[1:0]
Reserved, res0.

The TRCSTALLCTLR can be accessed through the external debug interface, offset 0x02c.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.