C10.16 ViewInst Start-Stop Control Register

The TRCVISSCTLR characteristics are:

Purpose
Defines the single address comparators that control the ViewInst Start/Stop logic.
Usage constraints
  • You must always program this register as part of trace unit initialization.
  • Accepts writes only when the trace unit is disabled.
Configurations
Available in all configurations.
Attributes
See C10.1 ETM register summary.
Figure C10-15 TRCVISSCTLR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


[31:24]
Reserved, res0.
STOP, [23:16]

Defines the single address comparators to stop trace with the ViewInst Start/Stop control.

One bit is provided for each implemented single address comparator.

[15:8]
Reserved, res0.
START, [7:0]

Defines the single address comparators to start trace with the ViewInst Start/Stop control.

One bit is provided for each implemented single address comparator.

The TRCVISSCTLR can be accessed through the external debug interface, offset 0x088.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.