C10.39 Single-Shot Comparator Control Register 0

The TRCSSCCR0 characteristics are:

Purpose
Controls the single-shot comparator.
Usage constraints
Accepts writes only when the trace unit is disabled.
Configurations
Available in all configurations.
Attributes
See C10.1 ETM register summary.
Figure C10-38 TRCSSCCR0 bit assignments
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[31:25]
Reserved, res0.
RST, [24]

Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected:

1Reset enabled. Multiple matches can occur.
[23:20]
Reserved, res0.
ARC, [19:16]

Selects one or more address range comparators for single-shot control.

One bit is provided for each implemented address range comparator.

[15:8]
Reserved, res0.
SAC, [7:0]

Selects one or more single address comparators for single-shot control.

One bit is provided for each implemented single address comparator.

The TRCSSCCR0 can be accessed through the external debug interface, offset 0x280.

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