C10.40 Single-Shot Comparator Status Register 0

The TRCSSCSR0 characteristics are:

Indicates the status of the single-shot comparator. TRCSSCSR0 is sensitive to instruction addresses.
Usage constraints
  • Accepts writes only when the trace unit is disabled.
  • The STATUS bit value is stable only when TRCSTATR.PMSTABLE==1.
Available in all configurations.
See C10.1 ETM register summary.
Figure C10-39 TRCSSCSR0 bit assignments
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STATUS, [31]

Single-shot status. This indicates whether any of the selected comparators have matched:

0Match has not occurred.
1Match has occurred at least once.

When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control.

Reserved, res0.
DV, [2]

Data value comparator support:

0Single-shot data value comparisons not supported.
DA, [1]

Data address comparator support:

0Single-shot data address comparisons not supported.
INST, [0]

Instruction address comparator support:

1Single-shot instruction address comparisons supported.

The TRCSSCSR0 can be accessed through the external debug interface, offset 0x2A0.

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