C10.44 Power Down Status Register

The TRCPDSR characteristics are:

Indicates the power down status of the ETM trace unit.
Usage constraints
There are no usage constraints.
Available in all configurations.
See C10.1 ETM register summary.
Figure C10-43 TRCPDSR bit assignments
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Reserved, res0.
OSLK, [5]

OS lock status.

0The OS Lock is unlocked.
1The OS Lock is locked.
Reserved, res0.

Sticky power down state.

0Trace register power has not been removed since the TRCPDSR was last read.
1Trace register power has been removed since the TRCPDSR was last read.

This bit is set to 1 when power to the ETM trace unit registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR.

POWER, [0]

Indicates the ETM trace unit is powered:

0ETM trace unit is not powered. The trace registers are not accessible and they all return an error response.
1ETM trace unit is powered. All registers are accessible.

If a system implementation allows the ETM trace unit to be powered off independently of the debug power domain, the system must handle accesses to the ETM trace unit appropriately.

The TRCPDSR can be accessed through the external debug interface, offset 0x314.

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