C10.51 Integration Instruction ATB Data Register

The TRCITIDATAR characteristics are:

Sets the state of the ATDATAMn output pins shown in the following table.
Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 1.
  • The value of the register sets the signals on the output pins when the register is written.
Available in all configurations.
See C10.1 ETM register summary.
Figure C10-50 TRCITIDATAR bit assignments
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For all non-reserved bits:

  • When a bit is set to 0, the corresponding output pin is LOW.
  • When a bit is set to 1, the corresponding output pin is HIGH.
  • The TRCITDDATAR bit values correspond to the physical state of the output pins.

Reserved, res0.

ATDATAM[31], [4]

Drives the ATDATAM[31] output.

ATDATAM[23], [3]

Drives the ATDATAM[23] output.

ATDATAM[15], [2]

Drives the ATDATAM[15] output.

ATDATAM[7], [1]

Drives the ATDATAM[7] output.

ATDATAM[0], [0]

Drives the ATDATAM[0] output.

The TRCITIDATAR can be accessed through the external debug interface, offset 0xEEC.

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