C10.57 Device Affinity Register 0

The TRCDEVAFF0 characteristics are:

Purpose

Provides an additional core identification mechanism for scheduling purposes in a cluster.

TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - RO RO RO RO RO
Configurations

The TRCDEVAFF0 is architecturally mapped to external TRCDEVAFF0 register.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
TRCDEVAFF0 is a 32-bit register.
Figure C10-56 TRCDEVAFF0 bit assignments
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M, [31]

Reserved, res1.

U, [30]

Indicates a single core system, as distinct from core 0 in a cluster. This value is:

0Processor is part of a multiprocessor system. This is the value for implementations with more than one core, and for implementations with an ACE or CHI master interface.
1Processor is part of a uniprocessor system. This is the value for single core implementations with an AXI master interface.
[29:25]

Reserved, res0.

MT, [24]

Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is:

0Performance of cores at the lowest affinity level is largely independent.
Aff2, [23:16]

Affinity level 2. Second highest level affinity field.

Indicates the value read in the CLUSTERIDAFF2 configuration signal.

Aff1, [15:8]

Affinity level 1. Third highest level affinity field.

Indicates the value read in the CLUSTERIDAFF1 configuration signal.

Aff0, [7:0]

Affinity level 0. Lowest level affinity field.

Indicates the core number in the Cortex®‑A32 processor. The possible values are:

0x0A processor with one core only.
0x0, 0x1A cluster with two cores.
0x0, 0x1, 0x2A cluster with three cores.
0x0, 0x1, 0x2, 0x3A cluster with four cores.

To access the TRCDEVAFF0:

MRC p15,0,<Rt>,c0,c0,5 ; Read TRCDEVAFF0 into Rt

Register access is encoded as follows:

Table C10-2 TRCDEVAFF0 access encoding

coproc opc1 CRn CRm opc2
1111 000 0000 0000 101

The TRCDEVAFF0 can be accessed through the external debug interface, offset 0xFA8.

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