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The TRCDEVAFF0 characteristics are:
Provides an additional core identification mechanism for scheduling purposes in a cluster.
TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
The TRCDEVAFF0 is architecturally mapped to external TRCDEVAFF0 register.
There is one copy of this register that is used in both Secure and Non-secure states.
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
|Processor is part of a multiprocessor system. This is the value for implementations with more than one core, and for implementations with an ACE or CHI master interface.|
|Processor is part of a uniprocessor system. This is the value for single core implementations with an AXI master interface.|
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is:
|Performance of cores at the lowest affinity level is largely independent.|
Affinity level 2. Second highest level affinity field.
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
Affinity level 1. Third highest level affinity field.
Indicates the value read in the CLUSTERIDAFF1 configuration signal.
Affinity level 0. Lowest level affinity field.
Indicates the core number in the Cortex®‑A32 processor. The possible values are:
|A processor with one core only.|
|A cluster with two cores.|
|A cluster with three cores.|
|A cluster with four cores.|
To access the TRCDEVAFF0:
MRC p15,0,<Rt>,c0,c0,5 ; Read TRCDEVAFF0 into Rt
Register access is encoded as follows:
Table C10-2 TRCDEVAFF0 access encoding
The TRCDEVAFF0 can be accessed through the external debug interface,