C10.58 Device Affinity Register 1

The TRCDEVAFF1 characteristics are:

The value is a read-only copy of MPIDR_EL1[63:32] as seen from EL3, unaffected by VMPIDR_EL2.
Usage constraints
Accessible only from the external debug interface.
Available in all configurations.

TRCDEVAFF1 is a 32-bit RO management register.

For the Cortex®‑A32 processor, MPIDR_EL1[63:32] is res0.

See C10.1 ETM register summary.

The TRCDEVAFF1 can be accessed through the external debug interface, offset 0xFAC.

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