|Non-Confidential||PDF version||ARM 100241_0001_00_en|
|Home > Debug > CTI registers > External register access permissions to the CTI registers|
External access permission to the cross trigger registers is subject to the conditions at the time of the access.
The following table describes the processor response to accesses through the external debug and memory-mapped interfaces.
Table C11-2 External register conditions
|Off||EDPRSR.PU is 0||
Processor power domain is completely off, or in a low-power state where the processor power domain registers cannot be accessed.
|DLK||EDPRSR.DLK is 1||OS Double Lock is locked.|
|OSLK||OSLSR_EL1.OSLK is 1||OS Lock is locked.|
||External debug access is disabled. When an error is returned because of an EDAD condition code, and this is the highest priority error condition, EDPRSR.SDAD is set to 1. Otherwise EDPRSR.SDAD is unchanged.|
|SLK||Memory-mapped interface only||Software lock is locked. For the external debug interface, ignore this row.|
|Default||-||None of the conditions apply, normal access.|
The following table shows an example of external register condition codes for access to a cross trigger register. To determine the access permission for the register, scan the columns from left to right. Stop at the first column a condition is true, the entry gives the access permission of the register and scanning stops.
Table C11-3 External register condition code example