C11.4 CTI Integration Mode Control Register

The CTIITCTRL characteristics are:

Purpose
The CTIITCTRL shows that the Cortex®‑A32 processor does not implement an integration mode.
Usage constraints

The accessibility of CTIITCTRL by condition code is:

Off DLK OSLK EDAD SLK Default
- - - - RO/WI RW

C11.2 External register access permissions to the CTI registers describes the condition codes.

Configurations
CTIITCTRL is in the Debug power domain.
Attributes
See the register summary in C11.1 Cross trigger register summary.
Figure C11-2 CTIITCTRL bit assignments
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[31:1]

Reserved, res0.

IME, [0]

Integration mode enable. The possible value is:

0Normal operation.

CTIITCTRL can be accessed through the external debug interface, offset 0xF00.

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