C11.5 CTI Peripheral Identification Registers

The CTI Peripheral Identification Registers provide standard information required for all components that conform to the ARM CoreSight architecture.

The following table lists the CTI Peripheral Identification Registers.

Table C11-4 Summary of the CTI Peripheral Identification Registers

Register Value Offset
Peripheral ID4 0x04 0xFD0
Peripheral ID5 0x00 0xFD4
Peripheral ID6 0x00 0xFD8
Peripheral ID7 0x00 0xFDC
Peripheral ID0 0xDB 0xFE0
Peripheral ID1 0xB9 0xFE4
Peripheral ID2 0x1B 0xFE8
Peripheral ID3 0x00 0xFEC

Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

Non-ConfidentialPDF file icon PDF versionARM 100241_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.