|Non-Confidential||PDF version||ARM 100241_0001_00_en|
|Home > Appendices > Signal Descriptions > About the signal descriptions|
The tables in this appendix provide direction information and high-level descriptions about the signals at the external interfaces of the processor.
Some of the buses include a configurable width field, <Signal>[CN:0], where CN = 0, 1, 2, or 3, to encode up to four cores. For example:
Some signals are specified in the form <signal>x where x = 0, 1, 2 or 3 to reference core 0, core 1, core 2, core 3. If a core is not present, the corresponding pin is removed. For example:
The number of signals changes depending on the configuration. For example, the CHI interface signals are not present when the processor is configured to have an ACE memory interface.