A.2 Processor configuration signals

The processor samples configuration signals only during cluster reset.

Table A-1 Processor configuration signals

Signal Direction Description
CFGEND[CN:0] Input

Endianness configuration at reset. It sets the initial value of SCTLR_EL3.EE and SCTR_S.EE:

0LOW.
1HIGH.
CFGTE[CN:0] Input

Enabling T32 exceptions. It sets the initial value of SCTLR.TE:

0LOW.
1HIGH.
CLUSTERIDAFF1[7:0] Input

Value read in MPIDR.Aff1.

This signal is sampled only during processor reset.

CLUSTERIDAFF2[7:0] Input

Value read in MPIDR.Aff2.

This signal is sampled only during processor reset.

CRYPTODISABLE[CN:0] Input

Disabling the Cryptographic Extensions.

VINITHI[CN:0] Input

Location of the exception vectors at reset. It sets the initial value of SCTLR.V:

0Exception vectors start at address 0x00000000.
1Exception vectors start at address 0xFFFF0000.
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