A.5 GIC signals

The processor uses a range of signals for global disable, base address definition, interrupt types, and Distributor messaging.

This interface exists only if the processor is configured to use the GIC CPU interface. However, the first seven signals in the following table are present even when the processor is configured without a GIC CPU interface.

Table A-4 GIC signals

Signal Direction Description
nFIQ[CN:0] Input

FIQ request. Active-LOW, level sensitive, asynchronous FIQ interrupt request:

0Activate FIQ interrupt.
1Do not activate FIQ interrupt.

The processor treats the nFIQ input as level-sensitive. The nFIQ input must be asserted until the processor acknowledges the interrupt.

nIRQ[CN:0] Input

IRQ request input lines. Active-LOW, level sensitive, asynchronous interrupt request:

0Activate interrupt.
1Do not activate interrupt.

The processor treats the nIRQ input as level-sensitive. The nIRQ input must be asserted until the processor acknowledges the interrupt.

nSEI[CN:0] Input

System Error Interrupt request. Active-LOW, edge sensitive:

0Activate SEI request.
1Do not activate SEI request.

The processor treats nSEI as edge-sensitive. The nSEI signal must be sent as a pulse to the processor.

Asserting the nSEI input causes an Asynchronous Data Abort. The DFSR.FS field is set to indicate an Asynchronous External Abort.

nVFIQ[CN:0] Input

Virtual FIQ request. Active-LOW, level sensitive, asynchronous FIQ interrupt request:

0Activate FIQ interrupt.
1Do not activate FIQ interrupt.

The processor treats the nVFIQ input as level-sensitive. The nVFIQ input must be asserted until the processor acknowledges the interrupt. If the GIC is enabled by tying GICCDISABLE LOW, nVFIQ must be tied off to HIGH. If the GIC is disabled by tying GICCDISABLE HIGH, nVFIQ can be driven by an external GIC in the SoC.

nVIRQ[CN:0] Input

Virtual IRQ request. Active-LOW, level sensitive, asynchronous interrupt request:

0Activate interrupt.
1Do not activate interrupt.

The processor treats nVIRQ as level-sensitive. nVIRQ must be asserted until the processor acknowledges the interrupt. If the GIC is enabled by tying GICCDISABLE LOW, nVIRQ must be tied off to HIGH. If the GIC is disabled by tying GICCDISABLE HIGH, nVIRQ can be driven by an external GIC in the SoC.

nVSEI[CN:0] Input

Virtual System Error Interrupt request. Active-LOW, edge sensitive:

0Activate virtual SEI request.
1Do not activate virtual SEI request.

The processor treats nVSEI as edge-sensitive. The nVSEI signal must be sent as a pulse to the processor.

Asserting nVSEI causes an asynchronous Data Abort. The DFSR.FS field is set to indicate an Asynchronous External Abort.

nREI[CN:0] Input

RAM Error Interrupt request. Active-LOW, edge sensitive:

0Activate REI request. Reports an asynchronous RAM error in the system.
1Do not activate REI request.

The processor treats nREI as edge-sensitive. The nREI signal must be sent as a pulse to the processor.

Asserting the nREI input causes an asynchronous Data Abort. The DFSR.FS field is set to indicate an Asynchronous parity error on memory access.

nVCPUMNTIRQ[CN:0] Output Virtual CPU interface maintenance interrupt PPI output.
PERIPHBASE[39:18] Input

Specifies the base address for the GIC registers. This value is sampled into CBAR at reset.

GICCDISABLE Input

Globally disables the GIC CPU interface logic and routes the external signals directly to the processor:

0Enable the GIC CPU interface logic.
1Disable the GIC CPU interface logic and route the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ signals directly to the processor. Drive this signal HIGH when you are using a legacy interrupt controller such as the GIC-400 which does not support GICv3 or GICv4.

Table A-5 AXI4 Stream Protocol signals for messages from the Distributor to the GIC CPU Interface

Signal Direction Description
ICDTVALID Input Indicates that the master is driving a valid transfer.
ICDTREADY Output Indicates that the slave can accept a transfer in the current cycle.
ICDTDATA[15:0] Input Primary payload for the data that is passing across the interface.
ICDTLAST Input Indicates the boundary of a packet.
ICDTDEST[1:0] Input Routing information for the data stream.

Table A-6 AXI4 Stream Protocol signals for messages from the GIC CPU Interface to the Distributor

Signal Direction Description
ICCTVALID Output Indicates that the master is driving a valid transfer.
ICCTREADY Input Indicates that the slave can accept a transfer in the current cycle.
ICCTDATA[15:0] Output Primary payload for the data that is passing across the interface.
ICCTLAST Output Indicates the boundary of a packet.
ICCTID[1:0] Output Data stream identifier.
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