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The processor has broadcast signals for the memory interface. These signals are only sampled at processor reset.
The signals in the following table only exist if the processor is configured to have an ACE or CHI memory interface.
Table A-17 Broadcast signals
Enable broadcasting of cache maintenance operations to downstream caches:
Enable broadcasting of Inner Shareable transactions:
If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER HIGH.
Enable broadcasting of outer shareable transactions: