A.10 Broadcast signals for the memory interface

The processor has broadcast signals for the memory interface. These signals are only sampled at processor reset.

The signals in the following table only exist if the processor is configured to have an ACE or CHI memory interface.

Table A-17 Broadcast signals

Signal Direction Description
BROADCASTCACHEMAINT Input

Enable broadcasting of cache maintenance operations to downstream caches:

0Cache maintenance operations are not broadcast to downstream caches.
1Cache maintenance operations are broadcast to downstream caches.
BROADCASTINNER Input

Enable broadcasting of Inner Shareable transactions:

0Inner Shareable transactions are not broadcast externally.
1Inner Shareable transactions are broadcast externally.

If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER HIGH.

BROADCASTOUTER Input

Enable broadcasting of outer shareable transactions:

0Outer Shareable transactions are not broadcast externally.
1Outer Shareable transactions are broadcast externally.
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