A.12 ACE interface signals

The ACE protocol supports clock, configuration, and data handling signals when the processor uses this protocol for the master memory interface.

This interface exists only if the Cortex®‑A32 processor is configured to have the ACE interface.

All ACE channels must be balanced with respect to CLKIN and timed relative to ACLKENM.

Table A-24 ACE clock and configuration signals

Signal Direction Description
ACLKENM Input ACE Master bus clock enable.
ACINACTM Input

Snoop interface is inactive and not participating in coherency:

0Snoop interface is active.
1Snoop interface is inactive.
RDMEMATTR[7:0] Output Read request memory attributes.
WRMEMATTR[7:0] Output Write request memory attributes.

Table A-25 ACE write address channel signals

Signal Direction Description
AWADDRM[43:0] Output Write address.
AWBARM[1:0] Output Write barrier type.
AWBURSTM[1:0] Output

Write burst type.

AWCACHEM[3:0] Output

Write cache type.

AWDOMAINM[1:0] Output Write shareability domain type.
AWIDM[4:0] Output Write address ID.
AWLENM[7:0] Output

Write burst length.

AWLOCKM Output

Write lock type.

AWPROTM[2:0] Output

Write protection type.

AWREADYM Input

Write address ready.

AWSIZEM[2:0] Output

Write burst size.

AWSNOOPM[2:0] Output

Write snoop request type.

AWUNIQUEM Output

For WriteBack, WriteClean and WriteEvict transactions.

Indicates that the write is:

0Shared.
1Unique.
AWVALIDM Output

Write address valid.

Table A-26 ACE write data channel signals

Signal Direction Description
WDATAM[127:0] Output Write data
WIDM[4:0] Output Write data ID
WLASTM Output Write data last transfer indication
WREADYM Input Write data ready
WSTRBM[15:0] Output Write byte-lane strobes
WVALIDM Output Write data valid

Table A-27 ACE write data response channel signals

Signal Direction Description
BIDM[4:0] Input Write response ID
BREADYM Output Write response ready
BRESPM[1:0] Input Write response
BVALIDM Input Write response valid

Table A-28 ACE read address channel signals

Signal Direction Description
ARADDRM[43:0] Output

Read address.

The top 4 bits communicate only the ACE virtual address for DVM messages.

The top 4 bits are Read-as-Zero if a DVM message is not being broadcast.

ARBARM[1:0] Output Read barrier type.
ARBURSTM[1:0] Output

Read burst type.

ARCACHEM[3:0] Output

Read cache type.

ARDOMAINM[1:0] Output Read shareability domain type.
ARIDM[5:0] Output Read address ID.
ARLENM[7:0] Output

Read burst length.

ARLOCKM Output

Read lock type.

ARPROTM[2:0] Output

Read protection type.

ARREADYM Input

Read address ready.

ARSIZEM[2:0] Output

Read burst size.

ARSNOOPM[3:0] Output

Read snoop request type.

ARVALIDM Output

Read address valid.

Table A-29 ACE read data channel signals

Signal Direction Description
RDATAM[127:0] Input Read data
RIDM[5:0] Input Read data ID
RLASTM Input Read data last transfer indication
RREADYM Output Read data ready
RRESPM[3:0] Input Read data response
RVALIDM Input Read data valid

Table A-30 ACE coherency address channel signals

Signal Direction Description
ACADDRM[43:0] Input

Snoop address.

The top 4 bits communicate only the ACE virtual address for DVM messages.

ACPROTM[2:0] Input

Snoop protection type.

ACREADYM Output

Master ready to accept snoop address.

ACSNOOPM[3:0] Input

Snoop request type.

ACVALIDM Input

Snoop address valid.

Table A-31 ACE coherency response channel signals

Signal Direction Description
CRREADYM Input

Slave ready to accept snoop response

CRVALIDM Output

Snoop response

CRRESPM[4:0] Output

Snoop response valid

Table A-32 ACE coherency data channel handshake signals

Signal Direction Description
CDDATAM[127:0] Output

Snoop data

CDLASTM Output

Snoop data last transform

CDREADYM Input Slave ready to accept snoop data
CDVALIDM Output Snoop data valid

Table A-33 ACE read and write acknowledge signals

Signal Direction Description
RACKM Output Read acknowledge
WACKM Output Write acknowledge
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