A.9 ACP interface signals

The AXI protocol supports clock, configuration, and data handling signals if the processor implements the ACP slave interface to an external master to make coherent request to the shared L2 cache of the cluster.

This interface exists only if the processor is configured to have the ACP interface.

All ACP channels must be balanced with respect to CLKIN and timed relative to ACLKENS.

Table A-11 ACP clock and Configuration signals

Signal Direction Description
ACLKENS Input AXI slave bus clock enable.
AINACTS Input

ACP master is inactive and is not participating in coherency. There must be no outstanding transactions when the master asserts this signal, and while it is asserted the master must not send any new transactions:

0ACP Master is active.
1ACP Master is inactive.

This signal must be asserted before the processor enters the low-power L2 WFI state.

Table A-12 ACP write address channel signals

Signal Direction Description
AWREADYS Output Write address ready
AWVALIDS Input Write address valid
AWIDS[4:0] Input Write address ID
AWADDRS[39:0] Input Write address
AWLENS[7:0] Input Write burst length
AWCACHES[3:0] Input Write cache type
AWUSERS[1:0] Input

Write attributes:

[0]Inner Shareable.
[1]Outer Shareable.
AWPROTS[2:0] Input Write protection type

Table A-13 ACP write data channel signals

Signal Direction Description
WREADYS Output Write data ready
WVALIDS Input Write data valid
WDATAS[127:0] Input Write data
WSTRBS[15:0] Input Write byte-lane strobes
WLASTS Input Write data last transfer indication

Table A-14 ACP write response channel signals

Signal Direction Description
BREADYS Input Write response ready
BVALIDS Output Write response valid
BIDS[4:0] Output Write response ID
BRESPS[1:0] Output Write response

Table A-15 ACP read address channel signals

Signal Direction Description
ARREADYS Output Read address ready
ARVALIDS Input Read address valid
ARIDS[4:0] Input Read address ID
ARADDRS[39:0] Input Read address
ARLENS[7:0] Input Read burst length
ARCACHES[3:0] Input Read cache type
ARUSERS[1:0] Input

Read attributes:

[0]Inner Shareable.
[1]Outer Shareable.
ARPROTS[2:0] Input Read protection type

Table A-16 ACP read data channel signals

Signal Direction Description
RREADYS Input Read data ready
RVALIDS Output Read data valid
RIDS[4:0] Output Read data ID
RDATAS[127:0] Output Read data
RRESPS[1:0] Output Read response
RLASTS Output Read data last transfer indication
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