A.15 APB interface signals

The debug APB bus supports clock, reset, addressing, and data handling signals when the processor includes an APB interface to provide access to the debug and performance monitoring registers.

You must balance all APB interface signals with respect to CLKIN and time them relative to PCLKENDBG.

Table A-43 APB interface signals

Signal Direction Description
nPRESETDBG Input

APB reset, active-LOW:

0Apply reset to APB interface.
1Do not apply reset to APB interface.
PADDRDBG[21:2] Input APB address bus.
PADDRDBG31 Input

APB address bus bit[31]:

0Not an external debugger access.
1External debugger access.
PCLKENDBG Input APB clock enable.
PENABLEDBG Input

Indicates the second and subsequent cycles of an APB transfer.

PRDATADBG[31:0] Output APB read data.
PREADYDBG Output

APB slave ready.

An APB slave can deassert PREADYDBG to extend a transfer by inserting wait states.

PSELDBG Input Debug bus access.
PSLVERRDBG Output

APB slave transfer error:

0No transfer error.
1Transfer error.
PWDATADBG[31:0] Input APB write data.
PWRITEDBG Input

APB read or write signal:

0Reads from APB.
1Writes to APB.
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