A.14 Debug signals

The processor has the following debug signals.

Table A-42 Debug signals

Signal Direction Description
DBGROMADDR[39:12] Input

Debug ROM base address.

Specifies bits[39:12] of the ROM table physical address.

If the address cannot be determined, tie this signal LOW.

This signal is sampled only during processor reset.

DBGROMADDRV Input

Debug ROM base address valid.

If the debug ROM address cannot be determined, tie this signal LOW.

This signal is sampled only during processor reset.

DBGACK[CN:0] Output

Debug acknowledge:

0External debug request not acknowledged.
1External debug request acknowledged.
nCOMMIRQ[CN:0] Output

Communications channel receive or transmit interrupt request

0Request interrupt.
1No interrupt request.
COMMRX[CN:0] Output

Communications channel receive. Receive portion of Data Transfer Register full flag:

0Empty.
1Full.
COMMTX[CN:0] Output

Communication transmit channel. Transmit portion of Data Transfer Register empty flag:

0Full.
1Empty.
EDBGRQ[CN:0] Input

External debug request:

0No external debug request.
1External debug request.

The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK.

DBGEN[CN:0] Input

Invasive debug enable:

0Not enabled.
1Enabled.
NIDEN[CN:0] Input

Non-invasive debug enable:

0Not enabled.
1Enabled.
SPIDEN[CN:0] Input

Secure privileged invasive debug enable:

0Not enabled.
1Enabled.
SPNIDEN[CN:0] Input

Secure privileged non-invasive debug enable:

0Not enabled.
1Enabled.
DBGRSTREQ[CN:0] Output Warm reset request.
DBGNOPWRDWN[CN:0] Output

Request not to power down the core:

0Do not request that the core stays powered up.
1Request that the core stays powered up.
DBGPWRUPREQ[CN:0] Output

Core power- up request:

0Do not request that the core is powered up.
1Request that the core is powered up.
DBGPWRDUP[CN:0] Input

Core powered up:

0Core is powered down.
1Core is powered up.
DBGL1RSTDISABLE Input

Disable the automatic invalidation of the L1 data cache at processor reset:

0Enable automatic invalidation of L1 data cache on reset.
1Disable automatic invalidation of L1 data cache on reset.

This signal is sampled only during processor reset.

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