A.19 CTI interface signals

The processor supports various cross-trigger signals when it implements the CTI.

Table A-47 CTI interface signals

Signal Direction Description
CTICHIN[3:0] Input Channel In
CTICHOUTACK[3:0] Input Channel Out acknowledge
CTICHOUT[3:0] Output Channel Out
CTICHINACK[3:0] Output Channel In acknowledge
CISBYPASS Input Channel interface sync bypass
CIHSBYPASS[3:0] Input Channel interface H/S bypass
CTIIRQ[CN:0] Output CTI interrupt, active-HIGH
CTIIRQACK[CN:0] Input CTI interrupt acknowledge
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