A.20 DFT interface signals

The processor uses the DFT signals to communicate with the external test device.

Table A-48 DFT interface signals

Signal Direction Description
DFTRAMHOLD Input Disable the RAM chip select during scan testing
DFTRSTDISABLE Input Disable internal synchronized reset during scan shift
DFTCGEN Input

Clock gate enable, forces on the clock grids during scan shift

DFTMCPHOLD Input Disable Multicycle Paths on RAM interfaces
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