B.3 Load/Store accesses crossing page boundaries

The Cortex®‑A32 processor implements a set of behaviors for load or store accesses that cross page boundaries.

Crossing a page boundary with different memory types or shareability attributes

The ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, states that a memory access from a load or store instruction that crosses a page boundary to a memory location that has a different memory type or shareability attribute results in constrained unpredictable behavior.

Crossing a 4KB boundary with a Device access

The ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, states that a memory access from a load or store instruction to Device memory that crosses a 4KB boundary results in CONSTRAINED UNPREDICTABLE behavior.

Implementation (for both page boundary specifications)

For an access that crosses a page boundary, the Cortex‑A32 processor implements the following behaviors:

  • Store crossing a page boundary:

    • No alignment fault.
    • The access is split into two stores.
    • Each store uses the memory type and shareability attributes associated with its own address.
  • Load crossing a page boundary (Device to Device and Normal to Normal):

    • No alignment fault.
    • The access is split into two loads.
    • Each load uses the memory type and shareability attributes associated with its own address.
  • Load crossing a page boundary (Device to Normal and Normal to Device):

    • The instruction might generate an alignment fault.
    • If no fault is generated, the access is split into two loads.
    • Each load uses the memory type and shareability attributes associated with its own address.
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