Part C Debug

Table of Contents

C1 Debug
C1.1 About debug methods
C1.2 Debug access
C1.3 Effects of resets on debug registers
C1.4 External access permissions to debug registers
C1.5 Debug events
C1.6 Debug memory map
C1.7 Debug signals
C1.8 Changing the authentication signals for debug
C2 PMU
C2.1 About the PMU
C2.2 External register access permissions to the PMU registers
C2.3 Performance monitoring events
C2.4 PMU interrupts
C2.5 Exporting PMU events
C3 ETM
C3.1 About the ETM
C3.2 Configuration options for the ETM unit and trace resources
C3.3 Resetting the ETM
C3.4 Programming and reading ETM trace unit registers
C4 CTI
C4.1 About the cross-trigger
C4.2 Cross-trigger inputs and outputs
C5 Direct access to internal memory
C5.1 About direct access to internal memory
C5.2 Encoding for tag and data in the L1 instruction cache
C5.3 Encoding for tag and data in the L1 data cache
C5.4 Encoding for the main TLB RAM
C5.5 Encoding for walk cache
C5.6 Encoding for IPA cache
C6 AArch32 debug registers
C6.1 AArch32 debug register summary
C6.2 Debug Breakpoint Control Registers
C6.3 Debug Watchpoint Control Registers
C6.4 Debug ID Register
C6.5 Debug Device ID Register
C6.6 Debug Device ID Register 1
C7 Memory-mapped debug registers
C7.1 Memory-mapped debug register summary
C7.2 External Debug Reserve Control Register
C7.3 External Debug Integration Mode Control Register
C7.4 External Debug Device ID Register 0
C7.5 External Debug Device ID Register 1
C7.6 External Debug Processor Feature Register
C7.7 External Debug Feature Register
C7.8 External Debug AArch32 Processor Feature Register
C7.9 External Debug Peripheral Identification Registers
C7.10 External Debug Peripheral Identification Register 0
C7.11 External Debug Peripheral Identification Register 1
C7.12 External Debug Peripheral Identification Register 2
C7.13 External Debug Peripheral Identification Register 3
C7.14 External Debug Peripheral Identification Register 4
C7.15 External Debug Peripheral Identification Register 5-7
C7.16 External Debug Component Identification Registers
C7.17 External Debug Component Identification Register 0
C7.18 External Debug Component Identification Register 1
C7.19 External Debug Component Identification Register 2
C7.20 External Debug Component Identification Register 3
C8 ROM table
C8.1 About the ROM table
C8.2 ROM table register interface
C8.3 ROM table register summary
C8.4 ROM entry registers
C8.5 ROM Table Peripheral Identification Registers
C8.6 ROM Table Peripheral Identification Register 0
C8.7 ROM Table Peripheral Identification Register 1
C8.8 ROM Table Peripheral Identification Register 2
C8.9 ROM Table Peripheral Identification Register 3
C8.10 ROM Table Peripheral Identification Register 4
C8.11 ROM Table Peripheral Identification Register 5-7
C8.12 ROM Table Component Identification Registers
C8.13 ROM Table Component Identification Register 0
C8.14 ROM Table Component Identification Register 1
C8.15 ROM Table Component Identification Register 2
C8.16 ROM Table Component Identification Register 3
C9 PMU registers
C9.1 AArch32 PMU register summary
C9.2 Performance Monitors Control Register
C9.3 Performance Monitors Common Event Identification Register 0
C9.4 Performance Monitors Common Event Identification Register 1
C9.5 Memory-mapped PMU register summary
C9.6 Performance Monitors Configuration Register
C9.7 Performance Monitors Peripheral Identification Registers
C9.8 Performance Monitors Peripheral Identification Register 0
C9.9 Performance Monitors Peripheral Identification Register 1
C9.10 Performance Monitors Peripheral Identification Register 2
C9.11 Performance Monitors Peripheral Identification Register 3
C9.12 Performance Monitors Peripheral Identification Register 4
C9.13 Performance Monitors Peripheral Identification Register 5-7
C9.14 Performance Monitors Component Identification Registers
C9.15 Performance Monitors Component Identification Register 0
C9.16 Performance Monitors Component Identification Register 1
C9.17 Performance Monitors Component Identification Register 2
C9.18 Performance Monitors Component Identification Register 3
C10 ETM registers
C10.1 ETM register summary
C10.2 Programming Control Register
C10.3 Status Register
C10.4 Trace Configuration Register
C10.5 Branch Broadcast Control Register
C10.6 Auxiliary Control Register
C10.7 Event Control 0 Register
C10.8 Event Control 1 Register
C10.9 Stall Control Register
C10.10 Global Timestamp Control Register
C10.11 Synchronization Period Register
C10.12 Cycle Count Control Register
C10.13 Trace ID Register
C10.14 ViewInst Main Control Register
C10.15 ViewInst Include-Exclude Control Register
C10.16 ViewInst Start-Stop Control Register
C10.17 Sequencer State Transition Control Registers 0-2
C10.18 Sequencer Reset Control Register
C10.19 Sequencer State Register
C10.20 External Input Select Register
C10.21 Counter Reload Value Registers 0-1
C10.22 Counter Control Register 0
C10.23 Counter Control Register 1
C10.24 Counter Value Registers 0-1
C10.25 ID Register 8
C10.26 ID Register 9
C10.27 ID Register 10
C10.28 ID Register 11
C10.29 ID Register 12
C10.30 ID Register 13
C10.31 Implementation Specific Register 0
C10.32 ID Register 0
C10.33 ID Register 1
C10.34 ID Register 2
C10.35 ID Register 3
C10.36 ID Register 4
C10.37 ID Register 5
C10.38 Resource Selection Control Registers 2-16
C10.39 Single-Shot Comparator Control Register 0
C10.40 Single-Shot Comparator Status Register 0
C10.41 OS Lock Access Register
C10.42 OS Lock Status Register
C10.43 Power Down Control Register
C10.44 Power Down Status Register
C10.45 Address Comparator Value Registers 0-7
C10.46 Address Comparator Access Type Registers 0-7
C10.47 Context ID Comparator Value Register 0
C10.48 VMID Comparator Value Register 0
C10.49 Context ID Comparator Control Register 0
C10.50 Integration ATB Identification Register
C10.51 Integration Instruction ATB Data Register
C10.52 Integration Instruction ATB In Register
C10.53 Integration Instruction ATB Out Register
C10.54 Integration Mode Control Register
C10.55 Claim Tag Set Register
C10.56 Claim Tag Clear Register
C10.57 Device Affinity Register 0
C10.58 Device Affinity Register 1
C10.59 Software Lock Access Register
C10.60 Software Lock Status Register
C10.61 Authentication Status Register
C10.62 Device Architecture Register
C10.63 Device ID Register
C10.64 Device Type Register
C10.65 ETM Peripheral Identification Registers
C10.66 ETM Peripheral Identification Register 0
C10.67 ETM Peripheral Identification Register 1
C10.68 ETM Peripheral Identification Register 2
C10.69 ETM Peripheral Identification Register 3
C10.70 ETM Peripheral Identification Register 4
C10.71 ETM Peripheral Identification Register 5-7
C10.72 ETM Component Identification Registers
C10.73 ETM Component Identification Register 0
C10.74 ETM Component Identification Register 1
C10.75 ETM Component Identification Register 2
C10.76 ETM Component Identification Register 3
C11 CTI registers
C11.1 Cross trigger register summary
C11.2 External register access permissions to the CTI registers
C11.3 CTI Device Identification Register
C11.4 CTI Integration Mode Control Register
C11.5 CTI Peripheral Identification Registers
C11.6 CTI Peripheral Identification Register 0
C11.7 CTI Peripheral Identification Register 1
C11.8 CTI Peripheral Identification Register 2
C11.9 CTI Peripheral Identification Register 3
C11.10 CTI Peripheral Identification Register 4
C11.11 CTI Peripheral Identification Register 5-7
C11.12 CTI Component Identification Registers
C11.13 CTI Component Identification Register 0
C11.14 CTI Component Identification Register 1
C11.15 CTI Component Identification Register 2
C11.16 CTI Component Identification Register 3
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