2.6 Media and VFP Feature Register 1

The MVFR1 characteristics are:

Purpose
Describes the features provided by the AArch32 Advanced SIMD and floating-point implementation.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - Config RO Config Config RO

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, HCPTR.{TCP10,TCP11}, and FPEXC.EN. For details of which values of these fields allow access at which exception levels, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile .

MVFR1 must be interpreted with MVFR0 and MVFR2. See 2.5 Media and VFP Feature Register 0 and 2.7 Media and VFP Feature Register 2

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
MVFR1 is a 32-bit register.
Figure 2-4 MVFR1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


SIMDFMAC, [31:28]

Indicates whether the Advanced SIMD and floating-point unit supports fused multiply accumulate operations:

0x1Implemented.
FPHP, [27:24]

Indicates whether the Advanced SIMD and floating-point unit supports half-precision floating-point conversion instructions:

0x2Instructions to convert between half-precision and single-precision, and between half-precision and double-precision, implemented.
SIMDHP, [23:20]

Indicates whether the Advanced SIMD and floating-point unit supports half-precision floating-point conversion operations:

0x1Implemented.
SIMDSP, [19:16]

Indicates whether the Advanced SIMD and floating-point unit supports single-precision floating-point operations:

0x1Implemented.
SIMDInt, [15:12]

Indicates whether the Advanced SIMD and floating-point unit supports integer operations:

0x1Implemented.
SIMDLS, [11:8]

Indicates whether the Advanced SIMD and floating-point unit supports load/store instructions:

0x1Implemented.
FPDNaN, [7:4]

Indicates whether the floating-point hardware implementation supports only the Default NaN mode:

0x1Hardware supports propagation of NaN values.
FPFtZ, [3:0]

Indicates whether the floating-point hardware implementation supports only the Flush-to-Zero mode of operation:

0x1Hardware supports full denormalized number arithmetic.

To access the MVFR1:

VMRS <Rt>, MVFR1 ; Read MVFR1 into Rt
Non-ConfidentialPDF file icon PDF versionARM 100243_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.