2.7 Media and VFP Feature Register 2

The MVFR2 characteristics are:

Purpose
Describes the features provided by the AArch32 Advanced SIMD and floating-point implementation.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - Config RO Config Config RO

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, HCPTR.{TCP10,TCP11}, and FPEXC.EN. For details of which values of these fields allow access at which exception levels, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile .

MVFR2 must be interpreted with MVFR0 and MVFR1. See 2.5 Media and VFP Feature Register 0 and 2.6 Media and VFP Feature Register 1

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
MVFR2 is a 32-bit register.
Figure 2-5 MVFR2 bit assignments
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[31:8]

Reserved, res0.

FPMisc, [7:4]

Indicates support for miscellaneous VFP features.

0x4

Supports:

  • Floating-point selection.
  • Floating-point Conversion to Integer with Directed Rounding modes.
  • Floating-point Round to Integral Floating-point.
  • Floating-point MaxNum and MinNum.
SIMDMisc, [3:0]

Indicates support for miscellaneous Advanced SIMD features.

0x3

Supports:

  • Floating-point Conversion to Integer with Directed Rounding modes.
  • Floating-point Round to Integral Floating-point.
  • Floating-point MaxNum and MinNum.

To access the MVFR2:

VMRS <Rt>, MVFR2 ; Read MVFR2 into Rt
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