2.8 Floating-Point Exception Control register

The FPEXC characteristics are:

Purpose
Provides a global enable for the Advanced SIMD and floating-point support, and indicates how the state of this support is recorded.
Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - Config RW Config Config RW

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, and HCPTR.{TCP10,TCP11}. For details of which values of these fields allow access at which exception levels, see the ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile .

Configurations

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes
FPEXC is a 32-bit register.
Figure 2-6 FPEXC bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


EX, [31]

Exception bit. The Cortex®‑A32 processor implementation does not generate asynchronous floating-point exceptions, therefore this bit is res0.

EN, [30]

Global enable for the Advanced SIMD and floating-point support:

0The Advanced SIMD and floating-point support is disabled. This is the reset value.
1The Advanced SIMD and floating-point support is enabled and operates normally.
[29:11]
Reserved, res0.
[10:8]
Reserved, res1.
[7:0]
Reserved, res0.

To access the FPEXC register:

VMRS <Rt>, FPEXC ; Read FPEXC into Rt
Non-ConfidentialPDF file icon PDF versionARM 100243_0001_00_en
Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved.