2.4.3 Snoop connectivity and control

The CCI-550 has a fully connected snoop interconnect and a snoop filter for efficient management of snoop request transactions.

The issuing of snoop requests and DVM message requests from a slave interface is controlled either:
Bit[29] of the Snoop Control Register for a slave interface indicates whether that interface is controlled using hardware or software.
A shareable read request from an ACE master allocates data to the cache of the master. This read request also allocates an entry in the snoop filter to record that the master has a copy of that data.
For requests that might require retrieval or invalidation of data in the cache of another master, the CCI-550 looks up the address in the snoop filter. If the snoop filter indicates that a master has a copy of that data, then:
If the snoop filter indicates that no ACE master contains that address, then the request is directed to the appropriate master interface. DVM requests are broadcast through all slave interfaces that are enabled for DVM messages and do not interact with the snoop filter.
You can configure the CCI-550 to have a single-layer or a dual-layer internal snoop data network. If there is a dual-layer network, you can use the Control Override Register to control whether it is used for data transfer between ACE masters.
The programmable bits of the Snoop Control Registers are LOW at reset. Program these bits HIGH for each master in the shareable domain before the CCI-550 receives shareable transactions or DVM messages. Before disabling a master, disable snoop and DVM messages for the master by programming the relevant bits of the Snoop Control Registers LOW.
If snoops are sent to interfaces where the master is disabled or not present, the system is likely to deadlock. The CCI-550 provides a hardware mechanism for disabling snoops. This mechanism prevents software errors causing deadlocks in cases where masters are not present or do not support DVMs. Each slave interface has an ACCHANNELENSx signal input. You can use ACCHANNELENSx to prevent the corresponding slave interface from issuing snoops or DVM messages, even if they are enabled by other means.

Note

These bits are sampled only at reset, and changing them after ARESETn is HIGH has no effect.

Removing a master from the coherent domain

To ensure correct system operation, you must follow a specific procedure to remove the master from the CCI-550 coherent domain before powering down your master.

Several steps in this procedure require actions on the processor that you want to power down. For these steps, see the appropriate processor documentation.

Procedure

  1. Configure the master so that it does not allocate shareable data into its cache, for example by disabling the data cache.
  2. Clean and invalidate all shareable data from the caches in the master.
  3. Disable the sending of snoops or DVM messages to the master. You can either use hardware control or program the Snoop Control Register, depending on your implementation.
  4. If you used the Snoop Control Register to disable snoops and DVM messages, ensure that the previous step is complete by executing a barrier instruction.
  5. Poll the Status Register to confirm that the Snoop Control Register changes are effected.

Postrequisites

After you complete these actions, the master is no longer in the coherent domain and you can power it down or disable it.

Adding a master to the coherent domain

To ensure correct system operation, you must follow a specific procedure to add a master to the CCI-550 coherent domain.

Before a master allocates any shareable data into its caches, you must add it to the CCI-550 coherent domain.

Procedure

  1. Enable the master to respond to snoops.
  2. Enable the sending of snoops or DVM messages to the master. Depending on your implementation, this is achieved either using hardware control or by programming the Snoop Control Register.
  3. Execute a barrier instruction to ensure that the previous step is complete.
  4. Poll the Status Register to confirm that the Snoop Control Register changes are effected.
  5. Configure the master so that it can issue cacheable, shareable transactions.
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