3.3.20 Master Interface Monitor Registers

These 32-bit RO registers monitor each master interface.

Usage constraints
There are no usage constraints.
Configurations
Available in all CCI-550 configurations.
An instance of this register exists for each master interface.
Attributes
See 3.2 Register summary for more information.
The following figure shows the bit assignments.
Figure 3-17 master_debug register bit assignments
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The following table shows the bit assignments.

Table 3-20 master_debug register bit assignments

Bits
Name
Function
[31:24]
-
Reserved.
[23:16]
outstanding_writes
Number of outstanding write transactions. From request handshake to response.
[15:8]
outstanding_reads
Number of outstanding read transactions. From request handshake to response.
[7:5]
-
Reserved.
[4]
stalled_b_channel
When this bit is set to 1, a transfer is stalled on the B channel, where both:
  • BVALID is HIGH.
  • BREADY is LOW.
[3]
stalled_w_channel
When this bit is set to 1, a transfer is stalled on the W channel, where both:
  • WVALID is HIGH.
  • WREADY is LOW.
[2]
stalled_aw_channel
When this bit is set to 1, a transfer is stalled on the AW channel, where both:
  • AWVALID is HIGH.
  • AWREADY is LOW.
[1]
stalled_r_channel
When this bit is set to 1, a transfer is stalled on the R channel, where both:
  • RVALID is HIGH.
  • RREADY is LOW.
[0]
stalled_ar_channel
When this bit is set to 1, a transfer is stalled on the AR channel, where both:
  • ARVALID is HIGH.
  • ARREADY is LOW.
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