A.3 Power and clock control signals

The CCI-550 uses a range of signals to communicate with the Q-Channel and P-Channel interfaces.

The following table shows the power and clock control signals.

Table A-3 Power and clock control signals

Signal
Direction
Description
AWAKEUPSx
Input
This signal must be driven HIGH when any of ARVALID, AWVALID, or WVALID are HIGH on the associated slave interface. When AWAKEUPSx is HIGH, the CCI-550 takes ACLKQACTIVE HIGH to request that the CCI clock is enabled.
There is one input for each slave interface, so that x = 0-6, depending on the configuration.
AWAKEUPMy
Output
HIGH when transfers are pending on the AR, AW, or W channels of the associated master interface. You can use this signal to request that the clock is turned on to downstream components.
There is one output for each master interface, so that y = 0-6, depending on the configuration.
PWAKEUP
Input
Indicates that the APB4 interface requires a clock because a transaction is incoming.
ACLKQREQn
Input
Request to disable the ACLK input. If the clock control channel is not used, then tie ACLKQREQn HIGH.
ACLKQACCEPTn
Output
Clock disable acceptance response.
ACLKQDENY
Output
Clock disable denial response.
ACLKQACTIVE
Output
Indicates that the CCI-550 requires the ACLK input to run.
PREQ
Input
Request to change power state.
PSTATE[2:0]
Input
Required power state.
The encodings for this input are:
0b000Off.
0b001Static snoop filter RAM retention.
0b010Reserved.
0b011Dynamic snoop filter RAM retention.
0b100On.
0b101-0b111Reserved.
If the P channel is not used, tie PSTATE to 0b100, On state.
PACCEPT
Output
Power state transition acceptance.
PDENY
Output
Power state transition denial.
PACTIVE[4:0]
Output
Hint from the CCI-550 to indicate the power states that it can accept.
Each bit corresponds to a power state. If the bit is HIGH, the state is a legal power transition:
[0]Off.
[1]Static snoop filter RAM retention.
[2]Reserved.
[3]Dynamic snoop filter RAM retention.
[4]On.
Non-ConfidentialPDF file icon PDF versionARM 100282_0100_00_en
Copyright © 2015, 2016 ARM. All rights reserved.