A.7 APB4 signals

The following table shows the APB4 slave interface signals. These signals are clocked using ACLK and reset using ARESETn.

Table A-7 APB4 signals

Signal
Direction
Description
PADDR[31:0]
Input
Address.
PPROT[2:0]
Input
Protection type.
PSEL
Input
Peripheral select.
PENABLE
Input
Enable for transfer.
PWRITE
Input
Write transaction indicator.
PWDATA[31:0]
Input
Write data.
PSTRB[3:0]
Input
Write data strobe.
PREADY
Output
Transfer ready.
PRDATA[31:0]
Output
Read data.
PSLVERR
Output
Error response.
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