ARM CoreLink CCI-550 Cache Coherent Interconnect Technical Reference Manual : 2.2.7 Debug and performance monitoring interface

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ARM 100282_0100_00_en

ARM^® CoreLink™ CCI-550 Cache Coherent Interconnect Technical Reference Manual

Revision r1p0

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The CCI-550 supports debug and performance monitoring using a combination of standard signals and a dedicated error pin.

The CCI-550 includes standard ARM^® interface signals for:

In addition, the nERRIRQ output pin indicates a transaction error that cannot be signaled precisely.

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