3.2 Register summary

The register summary lists all CCI-550 registers and some key characteristics.

The following table shows the registers in offset order. The base address of the CCI-550 is not fixed, and can be different for any particular system implementation. Consult your SoC implementation documentation for more information. The offset of each register from the base address is fixed.

Table 3-1 Register summary

Offset
Name
Type
Reset
Width
Description
0x00000
ctrl_ovr
RW
0x00000000
32
0x00008
secr_acc
RW
0x00000000
32
0x0000C
status
RO
0x00000000

Note

Assuming requested power state is OFF at reset.
32
0x00010
impr_err
RW
0x00000000
32
0x00014
qos_threshold
RW
QOS_THRESHOLD_UPPER
32
0x00100
pmu_ctrl
-
0x00004000
32
0x00104
debug_ctrl
RW
0x00000000
32
0x00FD0
peripheral_id4
RO
0x00000084
32
0x00FD4
peripheral_id5
RO
0x00000000
32
0x00FD8
peripheral_id6
RO
0x00000000
32
0x00FDC
peripheral_id7
RO
0x00000000
32
0x00FE0
peripheral_id0
RO
0x00000023
32
0x00FE4
peripheral_id1
RO
0x000000B4
32
0x00FE8
peripheral_id2
RO
0x0000003B
32
0x00FEC
peripheral_id3
RO
0x00000000
32
0x00FF0
component_id0
RO
0x0000000D
32
0x00FF4
component_id1
RO
0x000000F0
32
0x00FF8
component_id2
RO
0x00000005
32
0x00FFC
component_id3
RO
0x000000B1
32
Slave interface 0 registers
0x01000
snoop_ctrl
-
[31:29] IMPLEMENTATION DEFINED
[28:0] 0x00000000
32
0x01004
share_ovr
RW
0x00000000
32
0x01100
arqos_ovr
RW
0x00000000
32
0x01104
awqos_ovr
RW
0x00000000
32
0x01110
qos_max_ot
RW
IMPLEMENTATION DEFINED
32
Slave interface 1 registers
0x02000
snoop_ctrl
-
[31:29] IMPLEMENTATION DEFINED
[28:0] 0x00000000
32
0x02004
share_ovr
RW
0x00000000
32
0x02100
arqos_ovr
RW
0x00000000
32
0x02104
awqos_ovr
RW
0x00000000
32
0x02110
qos_max_ot
RW
IMPLEMENTATION DEFINED
32
Slave interface 2 registers
0x03000
snoop_ctrl
-
[31:29] IMPLEMENTATION DEFINED
[28:0] 0x00000000
32
0x03004
share_ovr
RW
0x00000000
32
0x03100
arqos_ovr
RW
0x00000000
32
0x03104
awqos_ovr
RW
0x00000000
32
0x03110
qos_max_ot
RW
IMPLEMENTATION DEFINED
32
Slave interface 3 registers
0x04000
snoop_ctrl
-
[31:29] IMPLEMENTATION DEFINED
[28:0] 0x00000000
32
0x04004
share_ovr
RW
0x00000000
32
0x04100
arqos_ovr
RW
0x00000000
32
0x04104
awqos_ovr
RW
0x00000000
32
0x04110
qos_max_ot
RW
IMPLEMENTATION DEFINED
32
Slave interface 4 registers
0x05000
snoop_ctrl
-
[31:29] IMPLEMENTATION DEFINED
[28:0] 0x00000000
32
0x05004
share_ovr
RW
0x00000000
32
0x05100
arqos_ovr
RW
0x00000000
32
0x05104
awqos_ovr
RW
0x00000000
32
0x05110
qos_max_ot
RW
IMPLEMENTATION DEFINED
32
Slave interface 5 registers
0x06000
snoop_ctrl
-
[31:29] IMPLEMENTATION DEFINED
[28:0] 0x00000000
32
0x06004
share_ovr
RW
0x00000000
32
0x06100
arqos_ovr
RW
0x00000000
32
0x06104
awqos_ovr
RW
0x0000000
32
0x06110
qos_max_ot
RW
IMPLEMENTATION DEFINED
32
Slave interface 6 registers
0x07000
snoop_ctrl
-
[31:29] IMPLEMENTATION DEFINED
[28:0] 0x00000000
32
0x07004
share_ovr
RW
0x00000000
32
0x07100
arqos_ovr
RW
0x00000000
32
0x07104
awqos_ovr
RW
0x00000000
32
0x07110
qos_max_ot
RW
IMPLEMENTATION DEFINED
32
Performance counter 0 registers
0x10000
evnt_sel
RW
0x00000000
32
0x10004
ecnt_data
RW
0x00000000
32
0x10008
ecnt_ctrl
RW
0x00000000
32
0x1000C
ecnt_clr_ovfl
RW
0x00000000
32
Performance counter 1 registers
0x20000
evnt_sel
RW
0x00000000
32
0x20004
ecnt_data
RW
0x00000000
32
0x20008
ecnt_ctrl
RW
0x00000000
32
0x2000C
ecnt_clr_ovfl
RW
0x00000000
32
Performance counter 2 registers
0x30000
evnt_sel
RW
0x00000000
32
0x30004
ecnt_data
RW
0x00000000
32
0x30008
ecnt_ctrl
RW
0x00000000
32
0x3000C
ecnt_clr_ovfl
RW
0x00000000
32
Performance counter 3 registers
0x40000
evnt_sel
RW
0x00000000
32
0x40004
ecnt_data
RW
0x00000000
32
0x40008
ecnt_ctrl
RW
0x00000000
32
0x4000C
ecnt_clr_ovfl
RW
0x00000000
32
Performance counter 4 registers
0x50000
evnt_sel
RW
0x00000000
32
0x50004
ecnt_data
RW
0x00000000
32
0x50008
ecnt_ctrl
RW
0x00000000
32
0x5000C
ecnt_clr_ovfl
RW
0x00000000
32
Performance counter 5 registers
0x60000
evnt_sel
RW
0x00000000
32
0x60004
ecnt_data
RW
0x00000000
32
0x60008
ecnt_ctrl
RW
0x00000000
32
0x6000C
ecnt_clr_ovfl
RW
0x00000000
32
Performance counter 6 registers
0x70000
evnt_sel
RW
0x00000000
32
0x70004
ecnt_data
RW
0x00000000
32
0x70008
ecnt_ctrl
RW
0x00000000
32
0x7000C
ecnt_clr_ovfl
RW
0x00000000
32
Performance counter 7 registers
0x80000
evnt_sel
RW
0x00000000
32
0x80004
ecnt_data
RW
0x00000000
32
0x80008
ecnt_ctrl
RW
0x00000000
32
0x8000C
ecnt_clr_ovfl
RW
0x00000000
32
Slave Interface Monitor Registers
0x90000
slave_debug, slave interface 0
R0
0x00000000
32
0x90004
slave_debug, slave interface 1
RO
0x00000000
32
0x90008
slave_debug, slave interface 2
RO
0x00000000
32
0x9000C
slave_debug, slave interface 3
RO
0x00000000
32
0x90010
slave_debug, slave interface 4
RO
0x00000000
32
0x90014
slave_debug, slave interface 5
RO
0x00000000
32
0x90018
slave_debug, slave interface 6
RO
0x00000000
32
Master Interface Monitor Registers
0x90100
master_debug, master interface 0
RO
0x00000000
32
0x90104
master_debug, master interface 1
RO
0x00000000
32
0x90108
master_debug, master interface 2
RO
0x00000000
32
0x9010C
master_debug, master interface 3
RO
0x00000000
32
0x90110
master_debug, master interface 4
RO
0x00000000
32
0x90114
master_debug, master interface 5
RO
0x00000000
32
0x90118
master_debug, master interface 6
RO
0x00000000
32
Non-ConfidentialPDF file icon PDF versionARM 100282_0100_00_en
Copyright © 2015, 2016 ARM. All rights reserved.