3.3.2 Secure Access Register

This register controls whether only Non-secure transactions can read and program the CCI-550 registers.

Usage constraints
You can write to this register using Secure transactions only.
Available in all CCI-550 configurations.
See 3.2 Register summary for more information.


This register enables Non-secure access for all masters to the CCI-550 registers. This compromises the security of your system.
The following figure shows the bit assignments.
Figure 3-2 secr_acc register bit assignments
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The following table shows the bit assignments.

Table 3-3 secr_acc register bit assignments

[2] secure_observation_override
Secure observation override:
0Disabled. The PMU counts Secure events according to the SPIDEN and SPNIDEN signals.
1Enabled. The PMU counts both Secure and Non-secure events.
Debug monitor security override:
0Enable Non-secure access to the PMU and Interface Monitor Registers.
1Disable Non-secure access to the PMU and Interface Monitor Registers, unless overridden by bit[0].
Non-secure register access override:
0Disable Non-secure access to the CCI-550 registers.
1Enable Non-secure access to the CCI-550 registers.
Related reference
3.3.19 Slave Interface Monitor Registers
3.3.20 Master Interface Monitor Registers
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