3.3.6 Performance Monitor Control Register (PMCR)

This register controls the PMU.

Usage constraints
Accessible using both Secure and Non-secure accesses, unless you set bit[1] of the Secure Access Register to disable Non-secure accesses to this register.
Configurations
Available in all CCI-550 configurations.
Attributes
See 3.2 Register summary for more information.
The following figure shows the bit assignments.
Figure 3-6 pmu_ctrl register bit assignments
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The following table shows the bit assignments.

Table 3-7 pmu_ctrl register bit assignments

Bits
Name
Access
Function
[31:16]
-
-
Reserved.
[15:11]
number_of_counters
RO
Specifies the number of counters implemented.
[10:5]
-
-
Reserved.
[4]
EX
RW
Enables export of the events to the event bus, EVNTBUS, to permit an external monitoring block to trace events:
0Do not export EVNTBUS.
1Export EVNTBUS.
[3:2]
-
-
Reserved.
[1]
RST
RAZ/W
Performance counter reset:
0No action.
1Reset all performance counters to zero.
[0]
CEN
RW
Enable bit:
0Disable all event counters.
1Enable all event counters.
The following table shows the relationship between the debug enable inputs, NIDEN and DBGEN, and the PMCR register settings.

Note

In this table, X can be any value.

Table 3-8 Relationship between NIDEN and DBGEN, and PMCR register settings

NIDEN OR DBGEN PMCR.CEN PMCR.EX Event counters enabled Events exported
0 X X No No
1 0 X No No
1 1 0 Yes No
1 1 1 Yes Yes
Related reference
3.3.2 Secure Access Register
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