3.3.18 Overflow Flag Status Registers

These registers contain the state of the overflow flags for the event counters.

Usage constraints
There are no usage constraints.
Available in all CCI-550 configurations.
One register exists for each event counter.
See 3.2 Register summary for more information.
The following figure shows the bit assignments.
Figure 3-15 ecnt_clr_ovfl register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the bit assignments.

Table 3-18 ecnt_clr_ovfl register bit assignments

Event counter overflow flag:
0The counter has not overflowed.
1The counter has overflowed.
When writing to this register, any overflow flag that is written with a value of 0 is ignored, that is, no change. An overflow flag that is written with a value of 1 clears the counter overflow flag. The negated counter overflow bits are exported from the CCI-550 on the nEVNTCNTOVERFLOW[7:0] signal. You can use this signal to trigger interrupts. The MSB corresponds to the cycle count overflow.
Non-ConfidentialPDF file icon PDF versionARM 100282_0100_00_en
Copyright © 2015, 2016 ARM. All rights reserved.