3.4 Address map

The CCI-550 uses an address map to route requests from slave interfaces to master interfaces. It is supplied with an example address decoder, that defines a global address map. You can rewrite the address decoders to define any address map at implementation time and also reconfigure the decoders at reset-time.

There is an address decoder per slave interface for each of read and write requests. You can, for example, use the same address map for each, or have a different decoder per slave interface. Ensure that accesses to the same address are routed to the same slaves downstream of the CCI-550.


The following text and diagram describes the operation of the address decoder that is supplied with CCI-550. However, the implementer is permitted to modify the address decoder. See your platform documentation to determine the address map for a particular implementation.
The supplied example decoder defines address regions, as specified in the document Principles of ARM® Memory Maps. The CCI-550 physical address width is configurable from 32-48 bits. The example address map is defined up to 44 bits. If a request accesses a region where the address is greater than 44 bits, the CCI-550 generates a DECERR response. If your implementation uses a smaller address width, then some regions are not addressable. Figure 3-18 Example decoder address regions shows the region sizes and offsets, with associated ADDRMAP inputs and address width limits.
Figure 3-18 Example decoder address regions
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In the example decoder, accesses to reserved regions generate a DECERR response.
For each non-reserved region, accesses are mapped to one of the master interfaces, or can be striped across several master interfaces. The mapping is determined using configuration input signals, ADDRMAP, that are sampled at reset. In the example address map, there are three ADDRMAP bits per region, with the encoding defined as:

Table 3-21 Decoder mapping

Master interface 0
Master interface 1
Master interface 2
Master interface 3
Master interface 4
Master interface 5
Master interface 6, MI6
The behavior depends on the number of memory interfaces that are configured:
  • With one memory port, all accesses in the region are to that port.
  • With two memory ports, striping occurs across both ports.
  • With three memory ports, striping occurs across the two highest numbered ports.
  • With four or more memory ports, striping occurs across the four highest numbered ports.


When using the supplied address decoder, memory ports are the highest numbered master interfaces.
If the ADDRMAP input maps a region to a master interface that is not present, the CCI-550 generates a DECERR response for requests that target that region.
The example decoder uses a stripe size of 256 bytes.
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