1.4 Interfaces

The CCI-550 has several interfaces to connect it to a wider system.

The CCI-550 is highly configurable. You can select how many master and slave components to include in your system. The following figure shows an example CCI-550-based system.
Figure 1-1 Example system with a CCI-550
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In this example, slave interfaces S5 and S6 support the ACE protocol for connecting masters such as the Cortex®-A53 or Cortex-A72 processors. The CCI-550 manages full coherency and data sharing between L1 and L2 caches of all connected processor clusters. Optionally, you can use the AMBA Domain Bridge (ADB-400) between components to integrate multiple power domains or clock domains.
Slave interfaces S0-S4 support ACE-Lite and DVM signaling for connecting I/O coherent devices such as the Mali™-T860 GPU or the Mali-T880 GPU. You can use DVM signaling for MMUs such as the MMU-500.
You can use the APB4 slave programming interface to program the CCI-550 registers.
In the example, four AXI4 master interfaces are connected to compatible memory controllers for LPDDR4 and LPDDR3 memory. Interfaces M5-M2 show these connections.
Typically, up to two AXI4 master interfaces are connected to system components, as shown by interfaces M1 and M0.
Clock and power control is achieved using Q-Channel and P-Channel interfaces.
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