1.6 Configurable options
The CCI-550 is highly configurable and provides both design-time and reset-time configuration options.
Design-time configuration options enable you to meet your functional
requirements with the smallest possible area and power. At design-time, you can
- The number of slave and master interfaces.
- The number of pipeline stages on interfaces, to aid timing closure for
- Low latency mode, enabling you to remove one cycle of latency from
request paths between slave and master interfaces.
- Write buffering, to achieve trade-off between area and write
- Read buffering, to achieve a trade-off between area and
- Single-layer or dual-layer snoop data bandwidth, to
meet your expected use-case.
- The size of the TT, to achieve trade-off between performance and
- Address widths.
- ID widths.
- The burst splitting option for slave interfaces.
- User-defined signal widths.
- The snoop filter RAM capacity to match connected processor cache
- The transport of data checksums, for example, parity or ECC.
Reset-time configuration options enable you to change the functionality of
the interconnect for different applications. At reset-time, you can configure:
- QoS threshold, to define the transactions that are treated as high priority within the interconnect.
- The QoS value of read and write requests according to allocated
bandwidth, using QoS regulators.
- A custom address decoder, to implement any arbitrary addressing
address map includes options that you can use to interleave memory channels. Optionally, you
can implement your own address decoder that defines any arbitrary addressing scheme. The
CCI-550 includes assertions
that you can use with formal tools or in simulation to verify that your address decoder
adheres to CCI-550