1.7 Test features
The CCI-550 supports both scan cell insertion and MBIST methodologies for your SoC Design For Test (DFT) strategy. DFT control signals provide high coverage for your test strategy for the CCI-550 design and associated internal RAM cells.
The DFT control signals provide the following capabilities:
- Disabling of internal resets.
- Controlling architectural clock gating.
- Controlling of internal RAM chip-select, to preserve state.
- Controlling of internal RAM MBIST signals.
- Limiting of multi-cycle paths to enable delay testing.