A.4 Configuration signals

The CCI-550 samples configuration signals only when the ARESETn signal transitions from LOW to HIGH.

The following table shows the configuration signals.

Table A-4 Configuration signals

Configuration inputs that you can use to define the mapping scheme of the address decoder. In the example decoder, there are 3 bits for each of the possible nine address regions.


It is the reset sampled version of the ADDRMAP that is passed to the address decode irrespective of whether it is the ARM® supplied address map or a modified version.
If HIGH, the internally generated values override the ARQOS and AWQOS input signals. See 2.4.12 Quality of Service for more information.
One bit exists for each slave interface.
ACCHANNELENSx[1:0] for ACE interfaces
ACCHANNELENSx[0] for ACE-Lite interfaces
AC channel enables, one input per slave interface. These inputs override any software enables.
Bit[0], DVM message enable
This bit is encoded as follows:
0DVM messages are disabled.
1DVM messages are enabled.
Bit[1], Snoop enable
This bit applies to ACE interfaces only, and is encoded as follows:
0Snoop requests are disabled.
1Snoop requests are enabled.


Snoops and DVM messages must still be enabled in the Snoop Control Registers.
Controls whether an ACE-Lite slave interface supports the Ordered Write Observation property.


ACE interfaces do not support the Ordered Write Observation property. This input is ignored for ACE slave interfaces.
This bit is encoded as follows:
0Interface does not support Ordered Write Observation.
1Interface supports Ordered Write Observation.
One bit exists for each slave interface.
If HIGH, all incoming requests are split into 64-byte transfers, rather than shareable requests only. This signal has no effect on an interface where the SIx_BURST_SPLITTER parameter is set to 0.
One bit exists for each ACE-Lite slave interface.
If HIGH, indicates that this interface is protected under TZMP1 and uses NSAID. Snoop data from this ACE interface is not returned directly to any other initiator.
One input signal exists for each ACE slave interface.
This signal is present only when the non_secure_access_id_support configuration parameter is set to 1.
If HIGH, indicates that this master interface is connected to a component with both slave and master interfaces, where there is a dependency between them. For example, a PCIe root complex usually has a slave interface where completion of a write depends on the progress of transactions on its master interface.
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