A.8.1 Write address channel signals

These signals carry control information that describes the nature of the data to be transferred. The data is transferred between master and slave using either a read data channel or a write data channel.

The following table shows the write address channel signals.

Table A-8 Write address channel signals

Signal
Direction
Description
AWIDSx[n:0]
Input
Write address ID.
The width of this signal is IMPLEMENTATION DEFINED.
AWADDRSx[n:0]
Input
Write address.
The width of this signal is IMPLEMENTATION DEFINED.
AWREGIONSx[3:0]
Input
Write address region. If the master does not drive this signal, you can tie it LOW.
AWLENSx[7:0]
Input
Write burst length.
AWSIZESx[2:0]
Input
Write burst size.
AWBURSTSx[1:0]
Input
Write burst type.
AWLOCKSx
Input
Write lock type.
AWCACHESx[3:0]
Input
Write cache type.
AWPROTSx[2:0]
Input
Write protection type.
AWSNOOPSx[2:0]
Input
Write snoop request type.
AWDOMAINSx[1:0]
Input
Write domain.
AWQOSSx[3:0]
Input
Write QoS value.
AWUSERSx[n:0]
Input
Specified extension to AW payload.
The width of this signal is IMPLEMENTATION DEFINED.
NSAIDWSx[3:0]
Input Optional extension to AW payload, that transmits the Non-secure access identifier for a request.
AWVALIDSx
Input
Write address valid.
AWREADYSx
Output
Write address ready.
AWTRACESx
Input
Write trace input.
This signal is replicated on the corresponding BTRACESx output, for all writes except Evict transactions.
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