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| Home > Signal descriptions > ACE and ACE-Lite slave interface signals > Write data channel signals | ||||
Write data channel signals carry the write data from the master to the slave, and include the data bus and a byte lane strobe signal.
Table A-9 Write data channel signals
|
Signal
|
Direction
|
Description
|
|---|---|---|
|
WDATASx[127:0]
|
Input
|
Write data.
|
|
WSTRBSx[15:0]
|
Input
|
Write byte-lane strobes.
|
|
WLASTSx
|
Input
|
Write last. This signal indicates the last transfer in a write
burst.
|
|
WUSERSx[n:0]
|
Input
|
The specified extension to the W payload.
The width of this signal is IMPLEMENTATION DEFINED.
|
|
WCHECKSUMSx[n:0]
|
Input
|
An optional extension to the W payload that can transmit checksum
or parity information for the data.
The width of this signal is IMPLEMENTATION DEFINED.
|
|
WVALIDSx
|
Input
|
Write data is valid.
|
|
WREADYSx
|
Output
|
Write data is ready.
|
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